1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having an overlay measurement mark and a method of fabricating the same.
2. Discussion of the Related Art
With semiconductor devices being highly integrated in recent years, a density of patterns formed on a wafer is increased. Specifically, a pattern density in a cell region is very high in comparison with that of a peripheral circuit region. The device elements formed in the cell region or the peripheral circuit region are formed by repeatedly performing processes, such as thin film deposition, a photolithography process, and an etch process.
The photolithography process is performed by repeating, many times, a series of sequential operations including depositing photoresist on a wafer to form a fine pattern on a wafer, exposing the deposited photoresist to transfer a circuit pattern formed on a reticle mask, and developing the exposed photoresist. When the operations of the photolithography process are repeatedly performed, it is necessary to match the patterns formed by a previous process with locations of patterns to be formed in a current process. This is because it is required that a wafer be placed at the same position as in a former pattern formation process in order to transfer a mask pattern of a reticle in a current process, so that interlayer patterns are precisely matched for electrical connection.
In the general semiconductor device fabrication processes, an overlay measurement mark is used to examine whether the patterns formed on an upper layer are matched with the patterns formed on a lower layer. In the conventional method, after box-type or frame-type main scale patterns are formed in a scribe line region in the process of forming a lower pattern, and an upper thin film is deposited thereon, when a photosensitive layer pattern to form a chip pattern is formed, a photosensitive layer pattern to be used as a box-type or frame-type vernier scale pattern is formed inside the main scale patterns, and an overlay between the main scale patterns and the vernier scale patterns is measured.
FIGS. 1A and 2A are plan views illustrating a conventional semiconductor device having an overlay measurement mark, and FIGS. 1B and 2B are sectional views taken along a line of I-I′ of FIGS. 1A and 2A, respectively.
Referring to FIGS. 1A and 1B, a main scale layer 15 having a trench box-shaped main scale pattern B1 is disposed on a semiconductor substrate 10. A box-shaped vernier scale pattern B2 is disposed inside the trench box-shaped main scale pattern B1 on the main scale layer 15. The main scale pattern B1 and the vernier scale pattern B2 constitute a box-in-box type overlay measurement mark.
The overlay measurement mark measures the degree that a thin film formed on a wafer in a former process overlays a thin film to be formed in a current process, by measuring a distance between the main scale pattern B1 and the vernier scale pattern B2. The overlay is divided into an x-axis overlay and a y-axis overlay, and the x-axis overlay and the y-axis overlay can be represented by a formula 1 and a formula 2 as follows respectively.x-axis overlay=(x1−x2)/2  [Formula 1]y-axis overlay=(y1−y2)/2  [Formula 2]
In the formula 1, “x1” and “x2” represent an x-axis distance between the main scale pattern B1 and the vernier scale pattern B2, and in the formula 2, “y1” and “y2” present a y-axis distance between the main scale pattern B1 and the vernier scale pattern B2.
Referring to FIGS. 2A and 2B, a main scale layer 25 having a trench frame-shaped main scale pattern F1 is formed on a semiconductor substrate 20. A frame-shaped vernier scale pattern F2 is disposed inside the frame pattern of the main scale pattern F1 on the main scale layer 25. The main scale pattern F1 and the vernier scale pattern F2 constitute a frame-in-frame type overlay measurement mark. The overlay measurement by the frame-in-frame type overlay measurement mark is made using the equation 1 and the equation 2 described in reference to FIGS. 1A and 1B.
As described above, in the case that the shape of the main scale is distorted due to procedure problems since one measurement mark exists in one region in the conventional box-type or frame-type, a possibility of producing defective semiconductor devices is increased because the measurement of an overlay is not made precisely.
Further, a technology is required to pattern a finer pattern at a more precise position with the increase in integration of semiconductor devices. In order to correspond to the requirements of highly-integrated semiconductor devices, fabrication equipment having a high numerical aperture (NA) of projection lens being capable of increasing a resolution may be employed, or development of light sources having shorter wave lengths such as use of an ArF laser beam may be required so as to form a much finer pattern. However, studies on an overlay measurement mark for exactly patterning at correct positions have not been developed as much as studies on development of resolution as above.
The box type or the frame type described in connection with FIGS. 1A and 2A has a limitation to measuring an overlay below 15 nm required to fabricate a semiconductor device under development below 70 nm. Since the box type or the frame type needs a vernier scale inside a main scale, it has a limitation to reducing a size of an overlay measurement mark. A size of the main scale, which is normally used in the box type or the frame type at present, is 30 to 40 μm, and the size of the main scale does not provide exact results for the overlay measurement below 15 nm required for the 70 nm or less semiconductor device. Further, as the scribe line region may be scaled down in consideration of mass production, a new overlay measurement mark being suitable to meeting the requirements is needed.